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NCP5383 2 Phase Buck Controller with Integrated Gate Drivers and AVP
The NCP5383 is a two phase buck controller used in low voltage, high current power supplies. Dual-edge pulse-width modulation (PWM) combined with inductor current sensing and adaptive voltage positioning (AVP) reduces system cost by providing the fastest initial response to transient loads thereby requiring less bulk and ceramic output capacitors to satisfy transient load-line requirements. A high performance operational error amplifier is provided, which allows for easy compensation of the system. Protection features include overcurrent protection, undervoltage lockout (UVLO), thermal shutdown and power good monitor.
Features http://onsemi.com MARKING DIAGRAM
1 24 PIN QFN, 4x4 MN SUFFIX CASE 485L 5383 ALYWG G
* * * * * * * * * * * *
Dual-edge PWM for Fastest Initial Response to Transient Loading High Performance Operational Error Amplifier 1% Internal Reference Voltage Accuracy Phase-to-Phase Current Balancing "Lossless" Differential Inductor Current Sensing Differential Current Sense Amplifiers for Each Phase Adaptive Voltage Positioning (AVP) Frequency Range: 100 kHz - 400 kHz Set by the Resistor Power Good Output with Internal Delays Programmable Soft Start Time Integrated Gate Drivers This is a Pb-Free Device
5383 A L Y W G
= Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
PG BST1 TG1 SWN1 PGND1 BG1 ROSC ILIM VCC AGND SS COMP VFB VDRP CS1 CSN CS2 EN (Top View) VCCP BG2 PGND2 SWN2 TG2 BST2
Applications
* Pentium IV Processors * Graphics Cards * Low Voltage, High Current Power Supplies
ORDERING INFORMATION
Device NCP5383MNR2G Package Shipping
QFN-24 4000 / Tape & Reel (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2007
1
December, 2007 - Rev. 3
Publication Order Number: NCP5383/D
NCP5383
SS Vcore
2
FAULT SS 23 BST1
OVP (125% of VFB) UVP (75% of VFB) FB 7 PG +
22
TG1
Gate Driver I
21 18
SWN1 VCCP
AGND 4 6 COMP 8 VDRP 9 10
0.8 V 19 Droop Amplifier + 0.8 V + + 13 20
BG1
PGND1
CS1 CSN CS2
BST2
14 11 + + 15 Gate Driver II VCCP 17
TG2
SWN2
ROSC
1
OSCILLATOR
BG2
ILIM
2
+ Fault Logic + UVLO
16 24
PGND2 PG
EN VCC
12 3 +
9V
Figure 1. Simplified Block Diagram
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NCP5383
VCC NCP5383 ROSC ILIM PG SS VCC VCCP BST1 3 18 23 12 V VCCP 1 2 24 5 5V
TG1 SWN1
22 21
Vcore
BG1
19
PGND1
20 VCCP VCC
7
VFB
BST2
13 14 15 Vcore
TG2 SWN2
6 8 9 10
COMP VDRP CS1
BG2
17
PGND2 CSN EN 11 CS2 AGND
16 12
4
Figure 2. Typical Application Schematic
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NCP5383
PIN DESCRIPTIONS
Pin No. 1 Symbol ROSC Description A resistance from this pin to ground programs the oscillator frequency according to fSW = 1 / (ROSC w 100 pF). Also, this pin supplies a trimmed output voltage of 2.00 V so it may be used to form a voltage divider at the ILIM pin to set the over current shutdown threshold as shown in the Applications Schematics. Over current shutdown threshold. To program the shutdown threshold, connect this pin to the ROSC pin via a resistor divider as shown in the Applications Schematics. To disable the over current feature connect this pin directly to the ROSC pin. To guarantee correct operation, this pin should only be connected to the voltage generated by the ROSC pin - do not connect this pin to any externally generated voltages. Power for the internal control circuits. Power supply return for the analog circuits that control output voltage. A capacitor from this pin to ground programs the soft-start time. Output of the error amplifier and input to the inverting pin of the PWM comparators. Voltage feedback pin and error amplifier inverting input. Connect a resistor from this pin to VCORE. The value of this resistor and the amount of current from the droop resistor (RDRP) will set the amount of output voltage droop (AVP) during load. Current signal output for Adaptive Voltage Positioning (AVP). The offset of this pin above the no-load set-point is proportional to the output current. Connect a resistor from this pin to VFB to set the amount of AVP current into the feedback resistor (RFB) that will result in output voltage droop. Leave this pin open for no AVP. Non-inverting input to current sense amplifier #x, x = 1, 2 Inverting input to current sense amplifier #x, x = 1 (Tie to VCORE) When this pin is pulled High the controller is enabled. When it is pulled Low the controller will be disabled. Either an open-collector output (with a pull-up resistor) or a logic gate (CMOS or totem-pole output) may be used to drive this pin. A Low to High transition on this pin will induce soft start. If the Enable function is not required, this pin should be tied directly to VCCP. Power for the gate drivers Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N-channel MOSFET.: Phase #x, x = 1, 2 Ground reference for the bottom gate drivers Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET. : Phase #x, x = 1, 2 Top gate MOSFET driver pin. Connect this pin to the gate of the top N-channel MOSFET. : : Phase #x, x = 1,2 Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the PHASE pin. Typical values for CBST range from 0.1 mF to 1 mF. Ensure that CBST is placed near the IC.: Phase #x, x = 1, 2. PowerGood output. Open drain type output with internal delays. The output is latched low if Vfb is 125% of VFB or 75% of VFB.
2
ILIM
3 4 5 6 7
VCC AGND SS COMP VFB
8
VDRP
9 10 12
CSx CSxN EN
18 19, 17 20, 16 21, 15 22, 14 23, 13
VCCP BG PGND SWN TG BST
24
PG
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NCP5383
ABSOLUTE MAXIMUM RATINGS
Rating Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Lead Temperature Soldering, Reflow (60 second maximum above 183C): Thermal Resistance, Junction-to-Ambient (RqJA) on a thermally conductive PCB in free air ESD Susceptibility (Human Body Model) JEDEC Moisture Sensitivity Level Maximum Voltage VCC with respect to AGND Maximum Voltage VCCP and all other pins with respect to ground Maximum Voltage VBST and all other pins with respect to ground Maximum Voltage VBST and all other pins with respect to SWN Maximum Voltage SWN and all other pins with respect to ground Minimum Voltage SWN and all other pins with respect to ground Minimum Voltage all pins with respect to ground Maximum Current into pins: COMP, VDRP Maximum Current out of pins: COMP, VDRP, ROSC, SS Value 0 to 70 0 to 125 -55 to 150 230 56 2.0 1 13.2 5.5 18.7 5.5 3.0 -2.0 -0.3 3.0 3.0 Unit C C C C C/W kV MSL V V V V V V V mA mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NCP5383
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 70C; 0C < TJ < 125C; 4.5 V < VCC < 13.2 V; Fsw = 400 KHz) Parameter Test Conditions Min Typ Max Units
Error Amplifier
Input Bias Current Input Offset Voltage Inverting Input Voltage Open Loop DC Gain Open Loop Unity Gain Bandwidth Open Loop Phase Margin Slew Rate 1.0 KW between VFB and COMP Pins CL = 100 pF to GND, RL = 10 KW to GND CL = 100 pF to GND, RL = 10 KW to GND CL = 100 pF to GND, RL = 10 KW to GND DVin = 100 mV, G = -1 V/V, DVout = 1.0 V - 2.0 V, CL = 10 pF to GND, Load = 125 mA to GND ISOURCE = 2.0 mA ISINK = 2.0 mA Vout = 3.0 V Vout = 1.0 V 3.0 -200 -1.0 792 800 78 15 65 5.0 -50 -10 1.0 808 nA mV mV dB MHz deg V/ms
Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 1) Output Sink Current (Note 1)
3.3 0.9 2.0 2.0 1.05
V V mA mA
Boost Current Supply Voltage
Input Voltage VCCP Operating Voltage VCCP 4.5 4.5 12 5.0 18 5.5 V V
VDRP Adaptive Voltage Positioning Amplifier
Current Sense Input to VDRP Gain Current Sense Input to VDRP Output Unity Gain Bandwidth Current Sense Input to VDRP Output Slew Rate CL = 330 pF to GND, RL = 10 KW to GND DVin = 100 mV, G = 6 V/V, DVout = 1.3 V - 1.9 V, CL = 330 pF to GND, Load = 400 mA to GND CSx - CSNx = 0, CSx = 1 V CSx - CSNx = 0.12 V, Isource = 1 mA CSx - CSNx = -0.12 V, Isink = 1 mA Vout = 1.2 V Vout = 1.0 V 9.0 2.0 1.2 0.5 5.7 6.0 7.2 6.3 V/V MHz
3.7
V/ms
Current Summing Amp Output Offset Voltage Maximum VDRP Output Voltage Minimum VDRP Output Voltage Output Source Current (Note 1) Output Sink Current (Note 1)
10
mV V V mA mA
Current Sense Amplifiers
Input Bias Current Common Mode Input Voltage Range Differential Mode Input Voltage Range Input Offset Voltage Current Sense Input to PWM Gain CSx = CSxN = 1.00 V 0 mV < (CSx- CSxN) < 25 mV TA = 25C CSx = CSxN = 1.4 V -200 -0.3 -120 -3.0 5.7 6.0 -50 -1.0 3.3 120 3.0 6.3 nA V mV mV V/V
1. Guaranteed by design, not tested in production.
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NCP5383
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 70C; 0C < TJ < 125C; 4.5 V < VCC < 13.2 V; Fsw = 400 KHz) Parameter Test Conditions Min Typ Max Units
Oscillator
Switching Frequency Range Switching Frequency Accuracy Switching Frequency Accuracy Switching Frequency Accuracy ROSC Output Voltage ROSC = 100 KW ROSC = 49.9 KW ROSC = 24.9 KW 100 90 180 360 1.92 100 200 400 2.00 400 110 220 440 2.08 KHz KHz KHz KHz V
Modulators (PWM Comparators)
Minimum Pulse Width (Note 1) Propagation Delay Magnitude of the PWM Ramp 0% Duty Cycle 100% Duty Cycle PWM Comparator Offset Mismatch Phase Angle Error PWM Linear Duty Cycle -15 90 COMP voltage when the PWM outputs remain LO COMP voltage when the PWM outputs remain HI Fs = 400 KHz 30 20 1.0 1.3 2.3 40 15 40 ns ns V V V Mv deg %
Gate Drivers
Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink Upper gate transition times Vbst - Vswn = 5 V, VTG - VSWN = 4 V Vbst - Vswn = 5 V, VTG - VSWN = 1 V VCCP = 5 V, Vgs = 4 V VCCP = 5 V, Vgs = 1 V Cload = 3 nF Cload = 3 nF Lower gate transition times Cload = 3 nF Cload = 3 nF SWN falling to BG rising delay BG falling to TG rising delay Cload = 3 nF Cload = 3 nF 1.8 1.8 1.8 0.9 16 16 16 7.0 18 40 W W W W ns ns ns ns ns ns
Soft-Start
Soft-Start Pin Source Current Soft-Start Pin Discharge Voltage Soft-Start Pin Discharge Time Fault = 1 From EN = 0 to VSS pin < max discharge voltage, CSS = 0.01 mF 5.0 5.0 50 mA mV ms
Enable Input
Enable High Input Leakage Current Upper Threshold Total Hysteresis EN = 3.0 V VUPPER VUPPER - VLOWER 0.80 50 0.85 100 10 0.90 150 mA V mV
Thermal Shutdown
Thermal Trip Point TSD 160 C
1. Guaranteed by design, not tested in production.
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NCP5383
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 70C; 0C < TJ < 125C; 4.5 V < VCC < 13.2 V; Fsw = 400 KHz) Parameter Test Conditions Min Typ Max Units
Current Limit
Current Sense Amp to ILIM Gain ILIM Pin Input Bias Current ILIM Pin Working Voltage Range ILIM Input Offset Voltage 20 mV < (Csx - CSxN) < 60 mV TA = 25C Vilim = 2.0 V 0.3 -50 5.7 6.0 0.1 6.3 1.0 2.0 50 V/V mA V mV
Undervoltage Protection
UVLO Start Threshold UVLO Stop Threshold UVLO Hysteresis UVLO Hysteresis VCCP = 5 V 3.7 VCC = 12 V 8.2 7.2 9.0 8.0 1.0 4.0 0.5 4.3 9.5 8.5 V V V V
Power Good
Output Saturation Voltage Rise Time IPG = 10 mA, VCC = 12 Vdc External pull-up of 1 KW to 1.25 V, CTOT = 45 pF, DVO = 10% to 90% External PG pull-up resistor of 2 KW to 5 V tR_VCC 3 x tR_5V, 100 ms tR_VCC 20 ms High - Output Leakage Current Upper Threshold Voltage Lower Threshold Voltage Rising Delay Falling Delay VCORE increasing VCORE decreasing 0.3 PG = 5.5 V via 1 K 125 75 1.40 5 2 0.1 mA % of VFB % of VFB ms ms 0.4 150 V ns
Output Voltage at Power-up
1.0
V
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NCP5383
TYPICAL CHARACTERISTICS
VCCP, UVLO THRESHOLD VOLTAGE (V) 408 405 fSW, FREQUENCY (kHz) 402 399 396 393 390 0 ROSC = 24.9 k VCC = 5.0 V 5.0
4.5 VCC Increasing Voltage 4.0 VCC Decreasing Voltage 3.5
3.0 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (C)
Figure 3. Oscillator Frequency vs. Temperature
Figure 4. UVLO Threshold Voltage vs. Temperature
10.8 10.7 ICC, CURRENT (mA)
SOFT-START SOURCING CURRENT (mA)
5.2
5.1
10.6 10.5 10.4 10.3 FSW = 400 kHz
5.0
4.9
4.8 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)
10.2 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)
Figure 5. Soft-Start Sourcing Current vs. Temperature
10 9.5 9.0 8.5 VCC Decreasing Voltage 8.0 7.5 7.0 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) VCC Increasing Voltage ICCP, CURRENT (mA) 16.8 16.5 16.2 15.9 15.6 15.3
Figure 6. ICC Current vs. Temperature
VCC UVLO THRESHOLD VOLTAGE (V)
FSW = 400 kHz 15.0 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)
Figure 7. VCC UVLO Threshold Voltage vs. Temperature
Figure 8. ICCP Current vs. Temperature
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NCP5383
TYPICAL CHARACTERISTICS
EN, ENABLE THRESHOLD VOLTAGE (V) 1.0 1.980 1.975 Enable Increasing Voltage ROSC VOLTAGE (V) 100 125 1.970 1.965 1.960 1.955 1.950 0 25 50 75 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
0.9
0.8 Enable Decreasing Voltage 0.7
0.6 0.5
Figure 9. Enable Threshold Voltage vs. Temperature
Figure 10. ROSC Voltage vs. Temperature
804 Vref, REFERENCE VOLTAGE (mV)
802
800
798
796 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)
Figure 11. Reference Voltage vs. Temperature
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NCP5383
Figure 12. 20 A Sustaining Load
Figure 13. UVLO Start
VCCP
Figure 14. UVLO Stop
Figure 15. Power-up Waveforms
VCCP
Figure 16. Soft Start Sequence
Figure 17. Power-down Waveforms
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NCP5383
APPLICATIONS INFORMATION
General
PROTECTION FEATURES
Undervoltage Lockout
The NCP5383 dual edge modulated multiphase PWM controller is specifically designed with the necessary features for a high current power system. The IC consists of the following blocks: High Performance Voltage Error Amplifier, Precision Oscillator and Triangle Wave Generators, and PWM Comparators. Protection features include Undervoltage Lockout, Soft-Start, Overcurrent Protection, Thermal Shutdown and Power Good Monitor.
High Performance Voltage Error Amplifier
An undervoltage lockout (UVLO) senses the VCC input. During powerup, the input voltage to the controller is monitored, and the PWM outputs and the soft-start circuit are disabled until the input voltage exceeds the threshold voltage of the UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering, since VCC is likely to decrease as soon as the converter initiates soft-start. There is a separate undervoltage lockout (UVLO) for the drivers that sense the VCCP inputs.
Overcurrent Shutdown
The error amplifier is designed to provide high slew rate and bandwidth. A capacitor from COMP to VFB is required for stable unity gain test configurations.
Oscillator and Triangle Wave Generator
A programmable precision oscillator is provided. The oscillator 's frequency is programmed by the resistance connected from the ROSC pin to ground. The user will usually form this resistance from two resistors in order to create a voltage divider that uses the ROSC output voltage as the reference for creating the current limit setpoint voltage. The oscillator frequency range is 100 kHz/phase to 400 kHz/phase. The oscillator generates 2 triangle waveforms (symmetrical rising and falling slopes) between 1.3 V and 2.3 V. The triangle waves have a phase delay between them such that for 2 phase operation the PWM outputs are separated by 180 degrees.
PWM Comparators with Hysteresis
Two PWM comparators receive the error amplifier output signal at their non inverting input. Each comparator receives one of the triangle waves offset by 1.3 V at it's inverting input. During steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by Vout/Vin. During a transient event, both high and low comparator output transitions shift phase to the points where the error amplifier output intersects the down and up ramp of the triangle wave.
A programmable overcurrent function is incorporated within the IC. A comparator and latch makeup this function. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin sets the maximum output current the converter can produce. The ROSC pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the ROSC pin sets the limit above useful levels - effectively disabling overcurrent shutdown. The comparator non inverting input is the summed current information from the current sense amplifiers. The overcurrent latch is set when the current information exceeds the voltage at the ILIM pin. The outputs are immediately, and the soft-start is pulled low. The outputs will remain disabled until the VCC voltage is removed and re-applied, or the ENABLE input is brought low and then high.
Power Good Monitor
NCP5383 has a power good monitor set at 125% of Vfb or 75% of Vfb for upper and lower thresholds respectively. It is an open drain type output.
Soft-Start
The NCP5383 incorporates an externally programmable soft-start. The soft-start circuit works by controlling the ramp-up of the Vref voltage during powerup. The initial soft-start pin voltage is 0 V. The soft-start sequence ends when VSS = 0.8 V. The soft-start pin is pulled to 0 V if there is an overcurrent shutdown, if VCC is below the UVLO threshold, or if VCCP is below the UVLO threshold.
Programming the Current Limit and Oscillator Frequency
The OSC pin provides a 2.0 V reference voltage which is divided down with a resistor divider and fed into the current limit pin ILIM. Calculate the total series resistance to set the frequency and then calculate the individual values for current limit divider. The series resistors RLIM1 and RLIM2 sink current to ground. This current is internally mirrored into a capacitor to create an oscillator. The period is proportional to the resistance and frequency is inversely proportional to the resistance.
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NCP5383
120 100 80 60 40 20 0 100 200 300 400 FREQUENCY (KHz)
ROSC (KW)
Calculate the current limit voltage: The current limit function is based on the total sensed current of two phases multiplied by a gain of 5.94. DCR sensed inductor current is function of the winding temperature. The best approach is to set the maximum current limit based on the expected average maximum temperature of the inductor windings.
DCRTmax + DCR25C * (1 ) 0.00393 * C-1 (TTmax-25 * C))
(eq. 1)
Figure 18. ROSC vs. Phase Frequency VILIMIT ^ 5.94 * IMIN_OCP * DCRTmax ) DCR50C * Vout * Vin-Vout * (N-1) * Vout L L 2 * Vin * Fs RLIM1 + ROSC-RLIM2 * 0.02
(eq. 2)
Solve for the individual resistors:
V * ROSC RLIM2 + ILIMIT 2*V Final Equation for the Current Limit Threshold ILIMIT(Tinductor) ^
2 * V * RLIM2 RLIM1)RLIM2
(eq. 3)
) 0.02
5.94 * (DCR25C * (1 ) 0.00393 * C-1(TInductor-25 * C)))
*
Vout * Vin-Vout * 1 * Vout 2 * Vin * Fs L L
(eq. 4)
Selecting the closest available values of 16.9 KW for RLIM1 and 15.8 KW yield a nominal operating frequency of 305 Khz and an approximate current limit of 180 A at 100C. The total sensed current can be observed at the VDRP pin added to a positive, no-load offset of approximately 0.8 V.
Inductor Selection:
When using the inductor current sensing it is recommended that the inductor does not saturate by more than 10% at the maximum load. The inductor also must not go into hard saturation before current limit trips. Small DCR values can be used, however current sharing accuracy and droop accuracy decrease as DCR decreases. Inductor Current Sense Compensation The NCP5383 uses the inductor current sensing method. This method uses an RC filter to cancel out the inductance of the inductor and recover the voltage that is the result of the current flowing through the inductor's DCR. This is done by matching the RC time constant of the current sense filter to the L/DCR time constant. The first cut approach is to use a 0.47 mF capacitor for C and then solve for R.
Rsense(T) +
(eq. 5)
Figure 19.
L 0.47 * mF * DCR25C * (1 ) 0.00393 * C-1 * (T-25 * C))
The demoboard inductor measured 950 nH and 0.75 mW at room temp. The actual value used for Rsense matches the equation for Rsense at approximately 50C. Because the inductor value is a function of load and inductor temperature final selection of R is best done experimentally on the bench by monitoring the Vdroop pin and performing a step load test on the actual solution. It is desirable to keep the Rsense resistor value below 1.0 k whenever possible by increasing the capacitor values in the inductor compensation network. The bias current flowing out of the current sense pins is approximately 100 nA. This current flows through the current sense resistor and creates an offset at the capacitor which will appear as a load current at the Vdroop pin. A 1.0 k resistor will keep this offset at the droop pin below 2.5 mV.
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NCP5383
Simple Average PSPICE Model A simple state average model shown in Figure 20 can be used to determine a stable solution and provide insight into the control system.
Figure 20.
Droop Injection The VDRP signal is generated by summing the sensed output currents for each phase and applying a gain of approximately six. VDRP is externally summed into the feedback network by the resistor RDRP. This induces an offset which is proportional to the output current thereby forcing the controlled resistive output impedance. RRDP determines the target output impedance by the basic equation:
Vout + Zout + RFB * DCR * 5.94 Iout RDRP RDRP + RFB * DCR * 5.94 Zout
(eq. 6)
Thermal Shutdown
The NCP5383 also provides Thermal Shutdown (TSD) for added protection. The TSD circuit monitors the die temperature and turns off the top and bottom gate drivers if an over temperature condition is detected. The internal soft-start capacitor is also discharged. This is a latched state and requires a power cycle to reset.
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NCP5383
PACKAGE DIMENSIONS
24 PIN QFN, 4x4 CASE 485L-01 ISSUE O
D
PIN 1 IDENTIFICATION
A B
E
2X
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.23 0.28 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.35 0.45
0.15 C
2X
0.15 C A2 0.10 C A
0.08 C
SEATING PLANE
A3 A1 D2
REF
C
DIM A A1 A2 A3 b D D2 E E2 e L
L
7 6 12
e
13
E2
24X
b
1 24 19
18
0.10 C A B 0.05 C
e
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5383/D

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